1. Field of the Invention: This invention is an architecture and a circuit for resolving to the lowest composite logical address (which address can contain non-unique priority and unique logical location information) among several competing parallel processors in a distributed processing computer communications system, in which many parallel processors are connected together via a multiprocessor intertie bus. Resolution is performed on the bus itself.
2. Description of the Prior Art: A prior art search uncovered the following references:
U.S. Pat. No. 4,096,569 provides priority resolution incorporating individual inhibit lines from each device to all lower priority devices, regardless of whether such devices are requesting access. The use of single valued inhibit lines in accomplishing parallel priority resolution requires many signal wires in the bus. The bus of the present invention uses ten signal lines to accomplish what would require 127 signal lines using the technique of this patent.
In U.S. Pat. Nos. 4,030,075, 3,993,981, and 4,120,029, priority resolution is dependent upon physical position along the bus, rather than the composite logical address, which can include priority and logical location (independent of physical location).
U.S. Pat. Nos. 3,800,287, 3,710,324, and 3,815,099 utilize daisy chaining priority resolution. This is a system in which processor "A" is matched against processor "B", the winner is pitted against processor "C", the winner of that is pitted against processor "D", etc. Daisy chaining is eschewed in the present invention because it introduces multiple single points of failure, and prohibits on-line bus adaptor replacement.
U.S. Pat. Nos. 4,128,883, 4,151,590, and 3,909,790 use centralized processing rather than distributed processing as in the present invention.
U.S. Pat. No. 4,004,283 employs sequential software polling for interrupt control, whereas the present invention eschews sequential polling. Furthermore, the patent requires hardwired Peripheral Interface Adapter identification in contrast to the logical addressing of the present invention.
U.S. Pat. No. 4,096,571 uses a single priority comparator to award priority to the device with the highest clock count on a wait-time bus. If there is a tie between two or more devices as to which has been waiting the longest, the tie is resolved by priority dummy source 19, which overrides the wait-time bus. On the other hand, the present invention resolves to the lowest composite logical address, comprised of non-unique priority information and unique logical location information. The present invention uses a single bus to perform priority resolution, data transfer, and addressing, whereas the patent uses three separate buses for these three functions.
The priority resolution network of U.S. Pat. No. 3,983,540 is inflexible and requires many signal wires. The present invention uses 10 signal prioritization lines to accomplish what would require 81 signal lines using the patent. Furthermore, the patent does not offer dynamic priority setting as does the present invention, and the patent has a priority network separate from the address/data bus, unlike in the present invention where all these functions are performed on the same bus.
Secondary references are: U.S. Pat. Nos. 4,020,471; 4,141,067; 4,058,711; 4,161,025; 4,118,771; 4,110,823; 4,106,090; and 4,048,623.
3. Related Patent:
U.S. Pat. No. 4,385,350, issued May 24, 1983.